The present invention relates to a semiconductor device, and more particularly to a technology that is effective in the application of semiconductor devices including a memory unit such as SRAM.
For example, Japanese Unexamined Patent Publication No. 2007-4960 discloses a configuration for reducing the voltage level of a cell power supply line when data is written in SRAM. Japanese Unexamined Patent Publication No. 2009-252256 discloses a configuration for reducing the voltage level of a selected word line in SRAM. Japanese Unexamined Patent Publication No. 2008-210443 discloses a configuration for supplying the power voltage level of a memory cell to a power supply node of a word line driver in the rise of the word line, and for supplying a voltage level, which is lower than the power voltage level of the memory cell, to the power supply node of the word line driver after the rise of the word line.